[專題演講] Toward scaling spin-based quantum processors with semiconductor technology
Toward scaling spin-based quantum processors with semiconductor technology
Prof. C.-Y. (Ted) Chang (張鑑元)
Institute of Electrical Engineering and Dept. of Physics, National Tsing Hua University
Date: 2025/09/30 (Tue)
Venue: S4-625
Time: 14:00-16:00
Abstract :
This talk will explore the potential of building a scalable quantum processing system with silicon-based spin qubits and peripheral processing units. We will introduce the basics of spin qubits, followed by recent advances in single- and two-qubit control as well as the engineering techniques in scaling spin-based qubit devices by RIKEN, Taiwan Semiconductor Research Institute (TSRI) and TSMC.
In the second part, we examine tailored Quantum Error-Correcting Codes (QECCs) for spin qubit processors, focusing on distance-3 surface and Bacon-Shor codes. We also present some of our recent progress in decoding error syndromes using Union Find algorithms. The algorithmic approach is implemented in our lab using an FPGA and will soon be tested in the TSMC N40 ASIC chip.